A robot designer cannot spend the same power saving twice: once on faster answers and again on longer battery life. DeepX’s newly taped-out DX-M2 makes that tradeoff concrete. Its projected memory-side acceleration is interesting, but the largest reported speedup is not a demonstration of that speed at an unchanged power budget.
According to EE Times’ November 9 report, DeepX designed the DX-M2 to run models with 20 billion to 100 billion total parameters, approximately 3 billion to 20 billion active, at 10–30 tokens per second depending on the model, within a roughly 5 W budget. These are design targets, not reported production measurements: samples are expected in March 2027, with mass production targeted for fall 2027.
The specific mechanism is processor-in-memory, or PIM. Instead of moving weights from memory to the accelerator for certain matrix-vector calculations, Samsung’s custom LPDDR5x-PIM can perform those operations inside the memory chip. For the operations offloaded this way, reducing that movement can relieve a memory-bandwidth bottleneck. DeepX’s simulation using Llama3.1-8B projects 6.7 times the tokens per second versus DX-M2 alone—but at 2.7 times the overall power consumption. Separately, the company thinks it can achieve twice the performance within the non-PIM power envelope.
Consider a hypothetical inspection robot whose operator requests a short explanation of a flagged defect. Faster generation could shorten the wait before the operator decides what to inspect next. But if the robot’s thermal allowance is fixed, the relevant opportunity would be the projected same-power improvement, not the maximum simulated speedup. Neither figure establishes longer operating time for the complete robot, which also powers movement, sensors and other computing.
The stronger product opportunity is therefore not simply putting the largest advertised model aboard a device. It is making a useful local response fit an existing power allowance. That could make an explanation feature more practical without requiring a larger thermal design; it would not establish better inspection judgment or eliminate connectivity needs elsewhere.
There is still a substantial dependency between that possibility and a product. EE Times reports a prototype compiler based on simulation, with physical testing hardware and compiler work unfinished. The decisive evidence will be useful response latency and total-system power on working hardware—not the parameter count alone.
